The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a wiring layer in contact holes of a semiconductor device.
The wiring method is regarded as being the most important matter of semiconductor device manufacturing technology, since it determines the performance (e.g., speed of operation), yield, and reliability of the devices. Metal step coverage was not a serious problem in less dense conventional semiconductor devices, because of the inherent features of devices having larger geometries, e.g., contact holes having a low aspect ratio (the ratio of depth to width) and shallow steps.
However, in recent years, with increased integration density in semiconductor devices, contact holes have become significantly smaller (having diameters less than half a micron) while impurity-doped regions formed in the surface portion of the semiconductor substrate have become much shallower. Due to the resulting higher aspect ratio of the contact holes and the larger steps with these greater-density semiconductor devices, it has become necessary to improve the conventional aluminum metallization process in order to achieve the standard design objectives of high-speed performance, high yield, and good reliability of the semiconductor device. In addition, the conventional method shows difficulty in filling contact holes having diameters less than 1 .mu.m and, therefore, creates a void in the contact hole of a semiconductor device.
In an effort to overcome the poor step coverage of aluminum, methods of filling in the contact holes by melting aluminum are disclosed in patent publications such as Japanese Laid-open Publication No. 62-132,848, Japanese Laid-open Publication No. 63-99,545 and Japanese Laid-open Publication No. 62-109,341. In addition, a method is disclosed in U.S. Pat. No. 4,907,176, in which a first metal layer is formed at a low temperature and another metal is deposited thereon to form a second metal layer while the temperature is increased, thereby improving the step coverage.
Moreover, the present inventor has invented a method comprising the steps of depositing an aluminum or an aluminum alloy at a low temperature to form a metal layer and heat-treating the metal layer in a vacuum at a high temperature (below the melting point), thereby reflowing the particles of the metal layer. An application therefore was filed on Sep. 19, 1990 (U.S. patent application Ser. No. 07/585,218 entitled "A Method for Forming a Metal layer in a Semiconductor Device") but has now been abandoned and a continuation-in-part (CIP) application thereof is pending in the USPTO as U.S. patent application Ser. No. 07/897,294.
In addition, during the initial stages of semiconductor manufacturing, pure aluminum was employed for forming the metal wiring layer, but as temperature increases in the sintering step, the aluminum layer absorbs the silicon atoms from the silicon substrate, and therefore the conventional method generates junction spiking. For this reason, Al-1%Si which is an aluminum supersaturated with silicon, is widely used as the material for the metal wiring layer.
However, if metal wiring of a semiconductor device is formed by the use of the above Al-1%Si, when heat-treating the semiconductor wafer at a temperature higher than about 450.degree. C. in a subsequent sintering step, Si from the Al film precipitates between the Al film and its adjacent layers form a solid state epitaxial Si-nodule in the contact holes, which may increase the resistance of a wiring layer or the contact resistance thereof.
To prevent the Al spiking due to the above-described reaction between the metal wiring layer and the silicon substrate or to prevent Si precipitations and Si-nodule formation, the formation of a diffusion barrier layers between the wiring layer and the silicon substrate or insulating layer has been suggested. For example, a method of forming a titanium nitride (TIN) film as the diffusion barrier layer on the inner surface of the contact hole is disclosed in U.S. Pat. No. 4,897,709 (Yokohama et al.). Moreover, in Japanese Laid-open Publication No. 61-183942, a method is disclosed wherein a double-layer composed of a refractory metal layer and a titanium nitride layer is formed as the barrier layer and then heat-treated. The titanium nitride layer reacts with the semiconductor substrate in the lower part of the contact hole connecting with the semiconductor substrate, so as to form the refractory metal silicide layer composed of thermally stable compounds, which can enhance the barrier effect and lower the contact resistance.
The formation of the aforementioned diffusion barrier layer becomes quite necessary due to the fact that the semiconductor device has been scaled down to dimensions of less than one micron. This diffusion barrier layer is generally heat-treated in order to improve the diffusion barrier characteristic. The process of heat-treating the diffusion barrier layer is conventionally performed by annealing the diffusion barrier layer under a nitrogen atmosphere. Unless the diffusion barrier layer is annealed, the junction spiking phenomenon may undesirably occur while sputtering Al or an Al-alloy at a temperature of 450.degree. C. or higher, or during the subsequent sintering thereof.
FIGS. 1 through 4 are sectional views showing an example of forming a wiring layer on the semiconductor substrate by the use of a conventional diffusion barrier layer.
FIG. 1 shows a step of implanting ions into the semiconductor substrate. More particularly, after forming a field oxide layer 3 on semiconductor substrate 1, for defining semiconductor substrate 1 into two parts, i.e., an active region and an isolation region, a pad oxide layer 5 is formed to a thickness of about 300 .ANG. by a thermal oxidation. Thereafter, As is implanted at a dose of 5.times.10.sup.15 atoms/cm.sup.2 to thereby form the n+ impurity-doped region, and BF.sub.2 is implanted at a dose of 5.times.10.sup.15 molecules/cm.sup.2 to thereby form the p+ impurity-doped region.
FIG. 2 shows an oxidation step. After the step of FIG. 1, an oxidation is performed at 950.degree. C. under a dry 0.sub.2 atmosphere. At this time, the doped impurities shown in FIG. 1 are first activated, so as to form the n+ and p+ impurity doped regions 7 and 8.
FIG. 3 shows a step of forming a contact hole. An insulating interlayer 9 is formed and the resultant structure is annealed at 950.degree. C. under N.sub.2 atmosphere for 240 minutes so that it is planarized. Here, the doped impurities are further activated. Thereafter, a contact hole 10 is formed in insulating interlayer 9 by a conventional photolithography process.
FIG. 4 shows steps of forming a diffusion barrier layer and forming a metal wiring layer thereon. After the step of FIG. 3, titanium and titanium nitride are deposited on the whole surface of the structure, so as to form the diffusion barrier layer composed of titanium layer 11 and titanium nitride 13. Thereafter, the wafer is annealed under a nitrogen atmosphere at a temperature of 450.degree. C. Then, on the diffusion barrier layer, an Al-Si-Cu alloy is deposited so as to form a metal layer, which is patterned by a photolithography process, so as to provide a wiring layer 15 of a semiconductor device. Thereafter, wiring layer 15 is sintered for thirty minutes at 400.degree. C.
When the metal wiring layer is formed on the diffusion barrier layer according to the aforementioned conventional method, titanium and titanium nitride exhibit poor step coverage with respect to a contact hole having a large aspect ratio (for example, greater than 1.2) and are easily oxidized in the annealing process in the furnace, thereby producing a higher contact resistance. This phenomenon becomes especially significant for contact holes having submicron dimensions.
For solving the above-mentioned problems (for example, in order to reduce the contact resistance in the p+ contact region), Yoshikawa et al. suggested a method which comprises forming the contact holes, ion-implanting BF.sub.2 at a dose of 1.times.10.sup.15 molecules/cm.sup.2 into the substrate, and then activating the p+ impurities by a rapid thermal annealing (RTA) for ten seconds or more at a temperature of 800.degree. C. or higher, to thereby decrease the contact resistance in the p+ contact region (see Semiconductor World, November 1989, pp. 36-38). However, this method is unsatisfactory because an additional two-step process (ion-implantation and activation) should be supplemented, so that the metal wiring process is so complicated that it can reduce the throughput of the semiconductor device.